1. Field of the Invention
The present invention relates to a dynamically reconfigurable field programmable gate array (FPGA).
2. Description of Related Art
FPGAs typically include configurable logic blocks (CLBs) which can be reconfigured to implement various logical functions. The configuration of these CLBs is defined by the data stored in a corresponding set of configuration memory cells. These configuration memory cells have been programmed in several different manners. Typically, the configuration memory cells are sequentially programmed in response to an externally provided stream of configuration data values. Newer technology, such as that described in U.S. Pat. No. 5,600,263, teaches that the configuration data values for a particular configuration can be stored in a separate memory within the FPGA. The separate memory is connected in parallel to each of the configuration memory cells. To reconfigure the FPGA, an entire set of configuration data values stored in the separate memory is simultaneously transferred from the separate memory to the configuration memory cells. As a result, the reconfiguration of the entire FPGA is virtually instantaneous. However, a relatively large amount of overhead is incurred in providing parallel connections between the separate memory and each of the configuration memory cells. In addition, because all of the configuration memory cells are loaded simultaneously, partial reconfiguration of the FPGA cannot be performed. Moreover, while conventional FPGAs can be configured to provide for small amounts of user RAM, the capacity of this user RAM is typically limited by the data storage capacity of function generators present within the CLBS.
It would therefore be desirable to have an FPGA which reduces the amount of routing resources required to reconfigure the FPGA. It would further be desirable to have an FPGA which can be readily partially reconfigured. It would also be desirable if such an FPGA were also capable of being reconfigured to provide a relatively large user RAM.